Caliber is having wide experience in designing custom Wirebond and Flipchip BGA package designs. Our engineers worked with many Fabs, Assembly and Test houses to produce best packages for the semiconductor devices. We also have in-house expertise to do electrical and thermal modeling as well as SI and PI analysis.
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| Technology selection |
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- Expertise in designing Flip-Chip, Wire Bond BGA and CSP
- Wire Bond
- Less cost and Flexible Process
- 2 - 6 Layer Substrate designs
- 4 layer results best performance
- Flip-Chip
- Allows for I/Os anywhere in the Die
- Assembly cost independent of # of I/Os
- Die shrink is possible compared to wire bond die
- Passive Integration in package
- Leaded packages, Array packages
- Design of MCMs
- Design of high pin count package
- Selection of Substrate Material
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| Design Challenges |
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- Growing complexity due to high speed signal
- Reflection and Ringing
- Optimal Power/GND Ball Placement & Plane Segmentation
- Inter-pair Crosstalk (Differential and Common mode)
- Propagation Delay Variations (skew)
- IR Drop, SSN and proper selection of De-coupling Caps
- Package Validation and Driver Models
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| required inputs |
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- Netlist
- Die Size & Pad Coordinates
- Package Type
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- Pin Use & Bus details
- Std I/O Library and Buffer SPICE models
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| Package Design Methodology |
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- Characteristic Impedance (Single Ended/Differential)
- Pair length match for LVDS, LVCMOS
- Max wirebond length and/or
max wirebond R and L
- Conductor – Conductor Xtalk,
- Conductor - Pair Xtalk,
- Pair - Pair Xtalk (all as % of Vdr)
(Differential and Common Mode)
- Physical Design Rules
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| planning & design |
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- Optimize Stack up and Routing for SI
- Best return paths for all IOs
- Power and Ground coupling
- Best isolation among sensitive signal groups
- Bump assignment Optimization:
- Optimal Power and GND
- Differential and Single Ended I/O
- Routing does not become impossible
- Power and Ground does not get chopped up
- SI driven Package pin out (GND-PWR vs. signals)
- Early SI start based on partial routing
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| Signal and Power Integrity |
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- Reflection and Ringing Analysis
- Propagation delay variations (skew)
- Single/differential Crosstalk Analysis
- EMI Analysis
- Single-ended I/O supply noise (SSN)
- Core Supply Noise & Analysis
- De-coupling Capacitors Estimation
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| Modeling (Electrical & Thermal) |
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- Parasitic RLC Extraction
- IBIS and S-parameter Model
- Thermal Analysis-Theta Ja, Jb and Jc
- Thermal Model and Nodal Temperature
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| Manufacturing Issues & CAM |
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- Good in-house CAM team
- Strict adherence to assembly and foundry specifications
- Material selection for Pre-preg and Solder Mask
- Coordination with assembly house and substrate foundry to achieve first time right substrate
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| package type |
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